1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a contact of a semiconductor device which efficiently removes an etching damage layer and a residual layer when fabricating a contact of a semiconductor memory device, thereby improving a motion characteristic of the device.
2. Background of the Related Art
Generally, in a device above 64M DRAM, a Self Aligned Contact(SAC) process is used when fabricating a contact which connects a capacitor and a cell transistor.
The Self Aligned Contact is formed by a dry etching process using a plasma. The plasma consists of free electrons generated by an RF discharge at a low pressure of 0.01xcx9c10 torr and etching gas ions, and is chemically very active to react with atoms of surrounding layers. If the plasma becomes volatile when reacted with the atoms of the surrounding layers, a compound of the plasma and the atoms is evaporated from the surface of a semiconductor substrate.
Meanwhile, when manufacturing a semiconductor device, a photoresist, a polysilicon layer, a metal layer or their layered film are also dry etched, and particularly, the metal layer is etched using a Cl2, and the polysilicon layer using SF6. A silicon oxide film (SiO2) is etched using CF4, and the photoresist using O2.
In this instance, since the SiO2 is used as an insulating layer between the capacitor and the cell transistor, the CF4 is used for etching the insulating layer. On the other hand, C4F8 is usually used in the SAC process.
The related art method for fabricating a contact of a semiconductor device will be described below with reference to the attached drawings.
FIGS. 1a to 1g illustrate sections showing the related art Process steps for fabricating a contact of a semiconductor device, and FIG. 2 illustrates a section showing a lower structure of a contact hole after performing a light etching for completely removing a plasma damage region.
First, as shown in FIG. 1a, a gate oxide film 3 is formed on a semiconductor 1, at which an active region and a device isolation region are defined by a field oxide film 2.
Subsequently, as shown in FIG. 1b, a doped polysilicon 4, a tungsten silicide (WSi) 5, and a nitride film (Si3N4) 6 are sequentially deposited on the gate oxide film 4.
Then, as shown in FIG. 1c, a photoresist (not shown) is applied on the nitride film 6, and is patterned by exposing and developing process. The oxide film 6, the tungsten silicide 5, the doped polysilicon 4, and the gate oxide film 3 are then selectively etched using the patterned photoresist film as a mask, to form gate and cap insulating layers 4a, 5a and 6a. 
Thereafter, a low concentration impurity ion is implanted using the gate and cap insulating layers 4a, 5a and 6a as masks, to form a low concentration impurity region 7 within a surface of the semiconductor substrate 1 at both sides of the gate, in order to be used as a Lightly Doped Drain (LDD).
Subsequently, as shown in FIG. 1d, a nitride film Si3N4 is deposited on an entire surface of the semiconductor substrate 1 which is exposed, including the gate and cap insulting layers 4a, 5a and 6a. The nitride film is then etched back, to form a gate sidewall 8 at sides of the gate and cap insulating layers 4a, 5a and 6a. Then, a high concentration impurity ion is implanted using the gate and cap insulating layers 4a, 5a and 6a, including the sidewall 8, as a mask, to form a source/drain region 9 of an LDD structure.
As shown in FIG. 1e, an insulating layer 10 is formed on an entire surface of the semiconductor substrate 1 including the gate and cap insulating layers 4a, 5a and 6a. Then, a photoresist 11 is applied thereon and is selectively patterned, to form a storage node contact mask.
As shown in FIG. 1f, the exposed insulating layer 10 is selectively etched by the SAC process using a plasma etching device, using the selectively patterned photoresist 11 as a mask, to form a contact hole 12. At this instance, a large quantity of carbon (C) ions are generated during the etching process, because the C4F8 is implanted within the etching device to induce the plasma. The C4F8 is used to improve an efficiency of the SAC process.
An SiC layer 13 is formed on a surface of the semiconductor substrate 1 by the carbon ions, at which a contact hole 12 is formed. Referring to an enlarged view of FIG. 1f, it is understood that a plasma damage layer 14 and the SiC layer 13 are formed at a bottom surface of the contact hole 12 (a surface of the semiconductor substrate), during the etching of plasma.
The SiC layer 13 is formed of a carbon component of the C4F8 and Si of the semiconductor substrate 1, and the plasma damage layer is a part in which Si gratings are damaged by a physical damage of the plasma.
The SiC layer 13 and the plasma damage layer 14 increase a contact resistance between a capacitor and a cell transistor which will be formed at a later process, as well as generating a leakage current.
Accordingly, as shown in FIG. 1g, a light etching process for removing the SiC layer 13 and the plasma damage layer 14 is performed after removing the photoresist 11, using an additional etching device having anisotropic low etching ratio.
During this light etching process, a substantial amount of O2 is used for preventing a re-formation of the SiC layer.
However, even if the process for removing the Sic layer 13 and the plasma damage layer 14 is performed using the light etch process, a residual SiC layer+plasma damage layer 15 is remained on a surface of the semiconductor substrate, as shown in an enlarged view of FIG. 1g. 
If, as shown in FIG. 2, a time of the light etching process is increased for removing the residual SiC+plasma damage layer 15, an isotropic etching ratio is increased accordingly even if the etching device having isotropic low etching ratio is used for the light etching process.
That is, inner parts of the source/drain region 9 with the LDD structure are dented, as in the part A shown in FIG. 2.
It is apparent that, by performing the light etching process in the SAC process, a restoration ratio of life time is improved.
FIG. 3 illustrates a change in the life time when using a TCA 3822 light etching device. As shown in the drawing, a time from excitation of electrons to extinction thereof is increased, if the light etching is performed with sufficient time. FIG. 3 illustrates a result of the light etching using only a source power, under a condition of 600 mTorr, 100 W, 45 O2 and 35 CF4.
However, the related art method for fabricating a contact of a semiconductor device has the following problems.
First, since an additional etching device having anisotropic low etching ratio is used for a long time instead of using an etching device used in the SAC process, a Turn Around Time (TAT) is increased and maintaining the device becomes difficult.
Second, in case of a general light etching process for removing the SiC layer and the plasma damage layer formed during the SAC process, a contact resistance is increased, as well as a leakage of current stored in the capacitor, because of the residual SiC layer+plasma damage layer.
As a result, a motion characteristic of a device is deteriorated. Particularly, in case of a memory device such as a DRAM, a reliability of the device is deteriorated because of inequality in refreshing movements, or reduction of refreshing time.
Finally, when the time of light etching is increased for removing the residual SiC layer and the plasma damage layer, the process becomes an isotropic etching. Accordingly, an inner part of the source/drain region with an LDD structure is damaged, thereby causing an inequality in the motion characteristic of the device, as well as deteriorating an yield.
Accordingly, the present invention is directed to a method for fabricating a contact of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a contact of a semiconductor device for efficiently removing an etching damage layer and a residual layer when fabricating a contact of a semiconductor memory device, thereby improving a motion characteristic of the device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for fabricating a contact of a semiconductor device in accordance with the present invention includes the steps of forming an insulating layer on a semiconductor substrate, forming a contact hole by selectively etching the insulating layer, so that a surface of the semiconductor substrate is exposed, primarily removing reaction by-products as well as a plasma damage layer at a bottom surface of a contact hole, with a pressure higher than that during the forming of the contact hole, and with a plasma source power and a bias power lower than those during the formation of the contact hole, and secondarily removing a residual plasma damage layer remaining after the primary removing step, by an anisotropic etching with a light etching process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.